1. Field of the Invention
Embodiments of the present invention relate to a method of forming a copper metal line of a semiconductor device and, more particularly, to a method of forming a copper metal line of a semiconductor device by employing a dual damascene process.
2. Background of the Invention
In general, when fabricating semiconductor devices, for electrical connection between elements or lines, metal lines are used. In recent years, as semiconductor devices are required to have higher integration and higher performance, copper (Cu), having more excellent electrical properties such as conductivity than aluminum (Al), is used as the material to form the metal lines.
A copper metal line is not easy to pattern through an etching process and is therefore patterned through a damascene process, instead of a subtractive patterning method that has generally been used to form aluminum metal lines. In a multi-line structure, a dual damascene process of forming a via connecting upper/lower lines and an upper metal line at the same time has been widely used.
In the dual damascene process, an intermetal dielectric layer is first deposited and formed. A dual damascene structure, comprised of trenches and a via, is formed within the intermetal dielectric layer by performing photolithography and subsequent etch processes twice. A copper film is gap-filled within the trenches and via, thereby making a polished surface. Thus, the copper film connects upper/lower lines through the via and forms an upper metal line within the trenches.
FIGS. 1a to 1i are process sectional views sequentially showing a conventional method of forming a copper metal line of a semiconductor device.
Referring first to FIG. 1a, a capping layer 120 is thinly deposited and formed on the entire upper surface of a substrate 110 in which lower lines 112 are formed. The capping layer 120 prevents metal atoms of the lower lines 112 from out-diffusing into an intermetal dielectric layer 130 subsequently formed over the capping layer 120 on the upper side.
The lower lines 112 defining a lower line region may be formed within the substrate 110 by forming trenches, gap-filling the trenches with a copper film, and polishing the resulting surface.
The capping layer 120 may be formed of silicon nitride (SiN, Si3N4) or other material having a hard film quality characteristic.
Referring next to FIG. 1b, the intermetal dielectric layer 130 is deposited and formed on the entire surface of the capping layer 120. The corresponding intermetal dielectric layer 130 functions to provide insulation between upper and lower lines, and may be formed of material with a low dielectric constant (low-k), such as a silicon oxide (SiO2) film, a doped silicon oxide film, or a fluorinated silica glass (FSG) film.
Referring next to FIG. 1c, a first photoresist pattern 140, having a first through-hole 140a at a location corresponding to a specific lower line 112, is formed on the intermetal dielectric layer 130 through, e.g., a typical photolithography process.
The photolithography process may comprise a series of processes, such as photoresist coating, exposure, and development.
Referring next to FIG. 1d, portions of the intermetal dielectric layer 130 and the capping layer 120 that are exposed by the first through-hole 140a of the first photoresist pattern 140 are removed by performing etching using the first photoresist pattern 140 as a mask. As a result, a via 132 may be vertically formed through which a surface of the lower line 112 is exposed.
The first photoresist pattern 140 is then removed through, e.g., an ashing process or the like.
Referring to FIG. 1e, a second photoresist pattern 150, having a second set of through-holes 150a defining an upper line region, is formed on the intermetal dielectric layer 130 through, e.g., a photolithography process. Each of the through-holes 150a may have a larger width than that of the via 132.
Referring to FIG. 1f, exposed upper portions of the intermetal dielectric layer 130 corresponding to the second set of through-holes 150a of the second photoresist pattern 150, are removed to a specific predetermined depth. The exposed portions are removed by performing etching using the second photoresist pattern 150 as a mask, thus forming trenches 134.
When forming the via 132 and the trenches 134 a dry etching process, such as reactive ion etching (RIE) which has an anisotropic characteristic, may be used.
Under certain conditions, the inside of the via 132 may become gap-filled with the second photoresist film. However, under such conditions a trenche 134 can still be formed over the via 132. As shown in the drawings, the trenches 134 are formed not only on the via 132, but also on a portion in which the via 132 is not formed.
Upon forming the trenches 134, the second photoresist pattern 150 is removed through, e.g., an ashing process or the like.
Accordingly, a dual damascene structure, having the trenches 134 on the upper side and the via 132 on the lower side, is formed.
Although the via etching process described above removes the exposed portions of both the intermetal dielectric layer 130 and the capping layer 120 at the same time (see FIG. 1d), the via 132 may instead be formed only within the intermetal dielectric layer 130, leaving the capping layer 120 temporarily intact. Then, after the trenches 134 are formed (see FIG. 1f), the portion of the capping layer 120 corresponding to the via 132 may be removed by a separate etching process.
Referring to FIG. 1g, a barrier metal film 160 is thinly deposited and formed on the entire surface, including inner walls of the via 132 and the trenches 134. The barrier metal film 160 functions to prevent copper atoms from diffusing when a copper metal line film 170 is subsequently formed, and may be made of, for example, tantalum (Ta) or tantalum nitride (TaN).
Referring to FIG. 1h, the copper metal line film 170 is fully gap-filled within the barrier metal film-coated via 132 and trenches 134 through, e.g., an electro chemical plating (ECP) process, so that the copper metal line film 170 is connected to the lower line 112. The ECP method has an excellent gap-filling characteristic, among other desirable physical properties.
Referring to FIG. 1i, the copper metal line film 170 and the barrier metal film 160, which are over-filled on the intermetal dielectric layer 130, are removed through a chemical mechanical polishing (CMP) process, thereby completing a copper metal line.
A surface of the copper metal line film 170 may then be polished, and a capping layer (not shown) may be deposited and formed on the entire surface of the copper metal line film 170.
Accordingly, the upper and lower lines are connected through the copper metal line film 170 within the via 132, and an upper line is formed with the copper metal line film 170 within the trenches 134.
However, the conventional copper metal line formation method has a number of problems.
For example, as shown in the scanning electron microscope (SEM) photograph of FIG. 2, the via 132 in contact with the lower line 112 can be misaligned (e.g., shifted to one side) relative to the lower line 112. Such misalignment can result from a mask alignment failure, for example, during the photolithography process. The trenches 134 can also be misaligned relative to the via 132 and/or the lower line 112. Therefore, a bridge phenomenon ‘B’ in which neighboring upper lines are interconnected can result.
If this bridge phenomenon ‘B’ occurs, a power short can occur upon subsequent use, which results in abrupt power loss, among other undesirable consequences. Accordingly, semiconductor devices with conventionally formed copper metal lines can have significantly degraded reliability.